This invention relates to the design of circuits for large scale integration (LSI) and very large scale integration (VLSI) circuit chips that use complementary metal oxide semiconductor (CMOS) technology. More particularly, the invention relates to the design of an improved CMOS circuit that combines a latch and shift register so as to remove a timing constraint that has been inherent in previous designs of such circuits.
The central processing unit (CPU) of a large computer system basically consists of latches, combinatorial logic, and a clocking system. The latches are arranged in sets, sometimes called registers, corresponding to the size of the word used within the computer system (a "word" is a prescribed number of bits). Between the sets of latches are combinatorial logic circuits, i.e., logic circuits that do not store data.
At the end of a clock cycle, which is also the beginning of the next clock cycle, the data on the output of the combinatorial logic circuitry is stored in a set of latches. This data appears on the output of the set of latches and therefore on the input of the combinatorial logic circuitry connected to the outputs of the set of latches. This logic circuitry performs the designed logic function on the data and at the end of the clock cycle, the output of the combinatorial logic is stored in the next set of latches. This process is repeated over and over as the computer system operates; that is, data is processed by combinatorial logic circuitry, stored, passed on to the next set of combinatorial logic circuitry, processed, stored, and so on.
With the advent of LSI and VLSI technologies, computer systems have become physically smaller. However, the availability of large numbers of logic circuits in small packages has allowed computer designers to incorporate features in the computer design that increase the reliability and testability of the system. Such features would have been considered too expensive prior to LSI and VLSI availability.
One of the features that is common in large computer systems today is a "scannable latch". A scannable latch includes a latch that can be converted to a stage of a shift register by the use of appropriate clock signals. The scannable latch further allows the contents of the resulting shift register to be "scanned" by shifting out the contents for examination. The shift register, and therefore the latch, can also be loaded with new contents by shifting new data thereinto.
When the above described latches are incorporated into the design, selected sets may be interconnected to form shift registers. At any time, the correct timing signals can stop the operation of the CPU and shift out the contents of the latches to an operator's computer console for examination; or a known set of data can be shifted into the latches from the computer console. Needless to say, this capability represents a powerful feature for testing a large computer. For example, if it is determined that the floating point division instruction is giving the wrong result, the latches involved can be loaded with a known set of numbers by shifting the known numbers thereinto. The CPU can then be allowed to carry out the calculation one cycle at a time. At the end of each cycle, the contents of the latches can be shifted out and checked. If the latches have the correct result, this result can be shifted back into the latches and the CPU is then allowed to execute the next cycle. This process is continued until an incorrect result is determined. The circuitry responsible for the incorrect result can then be readily found and replaced. In contrast, without this testing feature, isolating the faulty circuitry could be very difficult due to the large amount of circuitry and many clock cycles that are involved in the floating point division calculation.
CMOS VLSI technology allows a general purpose register (GPR) to be fabricated on a single chip: see e.g., copending patent application Ser. No. 468,602, filed 02/22/83, "Multiport General Purpose CMOS Register", attorney docket No. CRC-113, assigned to the same assignee as this application. A GPR, as its name implies, is a general purpose register which can be used, as needed, throughout a CPU for the temporary storage of data. Since the single chip GPR is relatively inexpensive and occupies a small amount of space, it may now be readily used within large computer systems; whereas before the advent of LSI and VLSI the GPR feature would have been considered too expensive.
A GPR may be used, as explained below, to store the history of the contents of the latches. This history may in turn be used to isolate circuit errors from random errors and perform other error detecting functions. For example, at the end of a clock cycle, when the outputs of the combinatorial logic circuitry are loaded into the latches, some selected set of these outputs may also be loaded into nearby GPR's. Thus, while the contents of the latches change every cycle, the GPR's contain a history of the previous contents of the latches. Further, error detecting logic may be designed into the combinatorial logic circuits, e.g., parity bits may be added to the word, parity generating and checking circuitry may be added to the combinatorial logic, and the outputs from redundant circuits may be added and their outputs checked to see if they are identical.
Hence, using the example of the floating point division instruction given above, if the error detecting circuitry detects an error after the fourth cycle of the calculation, the operation of the CPU can be halted and the data words from the GPRs that were stored four cycles previously may be loaded into the appropriate latches, at which time the CPU may be restarted. If the error was caused by some random failure mechanism, such as a noise pulse on the power distribution system, the second attempt at performing the calculation will be successful. This retry feature adds greatly to the reliability of the system since many of the errors will be random errors, and thus correctable errors.
If, however, the error was caused by a circuit failure, the error will occur again and the appropriate latches can then be scanned by the operator in an attempt to isolate the failing circuitry.
Unfortunately, while the above described error detection method greatly improves the reliability and testability of the computer system, only one half of the clock cycle is typically available to detect such errors. This is explained more fully below, but is basically caused by the fact that the clock signal must be in a prescribed state when the CPU operation is halted. If this time (when the clock is in its prescribed state) is not sufficient to detect the errors, the clock period must be extended, slowing down the operation of the computer system. What is needed, therefore, among other things, is a means for the errors to be detected at any time during the clock cycle, thereby preventing the operating speed of the computer system from being slowed down at the cost of reliability.